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| HCPL-520x, HCPL-523x, HCPL-623x, HCPL-625x, 5962-88768 and 5962-88769 Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers Data Sheet Description heeunitareingledualandquadchannelhermeti call ealed otocouler.he roduct are caable o oerationandtorageovertheullmilitartemerature rangeandcanbeurchaedaeithertandardroduct or with ull MP Cla evel or teting or rom the aroriate DSCC Drawing. ll device are manuacturedandtetedonaMPcertified lineandareincludedintheDSCCualifiedManuactur eritMorbridMicrocircuit. Each channel contain an la light emitting diode which i oticall couled to an integrated high gain hotondetector.hedetectorhaathreholdwithh tereiwhichrovidedifferentialmodenoieimmunit and eliminate the otential or outut ignal chatter. he detector in the ingle channel unit ha a tritate oututtagewhichallowordirectconnectiontodata bue.he outut i noninverting.he detector C ha aninternalhieldthatrovideaguaranteedcommon modetranientimmunitouto0000.mroved ower ul rejection eliminate the need or ecial owerulbarecaution. Features * DualMarkedwithDevicePartNumberandDSCC StandardMicrocircuitDrawing * Manuactured and eted on a MP Certi ManuacturedandetedonaMPCerti fiedine * M Cla and MClaand * our ermeticall Sealed Package Configuration ourermeticallSealedPackageConfiguration * Perormance uaranteed over C to C PerormanceuaranteedoverCtoC * ide CCange(.to0) ide * 0 n Maimum Proagation Dela 0nMaimumProagationDela * CM 0000 ical CM0000ical * 00 dc ithtand et oltage 00dcithtandetoltage * hree State utut vailable hreeStateututvailable * igh adiation mmunit ighadiationmmunit * CP00 unction Comatibilit CP00unctionComatibilit * eliabilit Data vailable eliabilitDatavailable * Comatible with S and CMS ogic ComatiblewithSandCMSogic Applications * * * * * * * * * MilitarandSace igheliabilitStem ranortationandieCriticalStem ighSeedineeceiver olatedBuDriver(SingleChannel) Puleranormerelacement roundooElimination arhndutrialEnvironment ComuterPeriheralnterace Note0.mbacaacitormutbeconnectedbetweenCCandNDin. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Functional Diagram MultileChannelDevicevailable V CC VO Truth Tables (Poitiveogic) Multichannel Devices Input On (H) Off (L) Output H L VE GND PackagetleortheeartareinDPthroughhole (caeoutlineP)6inDPflatack(caeoutline)and leadleceramicchicarrier(caeoutline).Devicema be urchaed with a variet o lead bend and lating otioneeSelectionuideableordetail.Standard MicrocircuitDrawing(SMD)artareavailableoreach ackageandleadtle. Becauetheameelectricaldie(emitteranddetector) are ued or each channel o each device lited in thi data heet abolute maimum rating recommended oeratingconditionelectricalecificationanderor mancecharacteritichowninthefigureareidentical orallart.ccaionalecetioneitduetoackage variationandlimitationandareanoted.dditionall theameackageaemblroceeandmaterialare uedinalldevice.heeimilaritiegivejutificationor theueodataobtainedromonearttorereentother art'erormanceordierelatedreliabilitandcertain limitedradiationtetreult. Single Channel Devices Input On (H) Off (L) On (H) Off (L) Enable H H L L Output Z Z H L Functional Diagrams 8 Pin DIP Through Hole 1 Channel 1 2 3 4 V CC VO 8 7 6 5 8 Pin DIP Through Hole 2 Channels 1 2 3 4 V CC V O1 V O2 8 7 6 5 1 2 3 4 5 6 7 8 16 Pin Flat Pack Unformed Leads 4 Channels 16 V CC V O1 V O2 V O3 V O4 GND 15 14 13 12 11 10 9 20 Pad LCCC Surface Mount 2 Channels 15 V CC2 19 20 V O2 GND 2 V O1 GND 1 7 8 V CC1 13 12 VE GND 2 3 10 GND NoteMultichannelDPandflatackdevicehavecommonCCandground.SinglechannelDPhaanenablein6.CCC(leadleceramicchi carrier)ackagehaiolatedchannelwithearateCCandgroundconnection. Selection Guide-Package Styles and Lead Configuration Options Package Lead Style Channels Common Channel Wiring Avago Technologies' Part Numbers and Options Commercial MIL-PRF-38534 Class H MIL-PRF-38534 Class K Standard Lead Finish Solder Dipped* Butt Joint/Gold Plate Gull Wing/Soldered* Class H SMD Part Number Prescript for all below Either Gold or Soldered Gold Plate Solder Dipped* Butt Joint/Gold Plate Butt Joint/Soldered* Gull Wing/Soldered* Class K SMD Part Number Prescript for all below Either Gold or Soldered Gold Plate Solder Dipped* Butt Joint/Gold Plate Butt Joint/Soldered* Gull Wing/Soldered* *Soldercontainlead 8 Pin DIP Through Hole 1 None 8 Pin DIP Through Hole 2 VCC GND HCPL-5230 HCPL-5231 HCPL-523K Gold Plate Option 200 Option 100 Option 300 16 Pin Flat Pack Unformed Leads 4 VCC GND HCPL-6250 HCPL-6251 HCPL-625K Gold Plate 20 Pad LCCC Surface Mount 2 None HCPL-5200 HCPL-5201 HCPL-520K Gold Plate Option 200 Option 100 Option 300 HCPL-6230 HCPL-6231 HCPL-623K Solder Pads * 59628876801PX 8876801PC 8876801PA 8876801YC 8876801YA 8876801XA 59628876901PX 8876901PC 8876901PA 8876901YC 8876901YA 8876901XA 59628876903FX 8876903FC 596288769022X 88769022A 59628876802KPX 8876802KPC 8876802KPA 8876802KYC 8876802KYA 8876802KXA 59628876904KPX 8876904KPC 8876904KPA 8876904KYC 8876904KYA 8876904KXA 59628876906KFX 8876906KFC 59628876905K2X 8876905K2A Outline Drawings 8 Pin DIP Through Hole, 1 and 2 Channel 9.40 (0.370) 9.91 (0.390) 0.76 (0.030) 1.27 (0.050) 4.32 (0.170) MAX. 0.51 (0.020) MIN. 8.13 (0.320) MAX. 7.16 (0.282) 7.57 (0.298) 3.81 (0.150) MIN. 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 16 Pin Flat Pack, 4 Channels 7.24 (0.285) 6.99 (0.275) 2.29 (0.090) MAX. 1.27 (0.050) REF. 11.13 (0.438) 10.72 (0.422) 0.46 (0.018) 0.36 (0.014) 2.85 (0.112) MAX. 8.13 (0.320) MAX. 0.89 (0.035) 0.69 (0.027) 5.23 (0.206) MAX. 0.88 (0.0345) MIN. 9.02 (0.355) 8.76 (0.345) 0.31 (0.012) 0.23 (0.009) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 20 Terminal LCCC Surface Mount, 2 Channels 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.02 (0.040) (3 PLCS) 1.14 (0.045) 1.40 (0.055) 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 0.64 (0.025) (20 PLCS) 1.52 (0.060) 2.03 (0.080) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.127 (0.005) MAX. 1.78 (0.070) 2.03 (0.080) TERMINAL 1 IDENTIFIER 2.16 (0.085) METALIZED CASTILLATIONS (20 PLCS) 0.51 (0.020) Leaded Device Marking AVAGO Designator AVAGO P/N DSCC SMD* DSCC SMD* PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX 50434 COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. AVAGO FSCN* *QUALIFIED PARTS ONLY Leadless Device Marking AVAGO Designator AVAGO P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. A QYYWWZ XXXXXX XXXX XXXXXX XXX 50434 COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) DSCC SMD* DSCC SMD* AVAGO FSCN* *QUALIFIED PARTS ONLY Hermetic Optocoupler Options Option 100 Description Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). 4.32 (0.170) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) 200 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads. 4.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390) 4.57 (0.180) MAX. 300 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 5 MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Note: Soldercontainlead Absolute Maximum Ratings Parameter Storageemeratureange eratingmbientemerature Junctionemerature Caeemerature eadSolderemerature (.6mmbeloweatinglane) verageorwardCurrenteachchannel PeaknutCurrenteachchannel everenutoltageeachchannel verageututCurrenteachchannel Suloltage ututoltageeachchannel PackagePowerDiiationeachchannel P CC PD 0.0 0. Symbol S J C Min. 6 Max. 0 7 70 60or0 0[] 0 0 00 Units C C C C C m m m m Single Channel Product Only riStateEnableoltage E 0. 0 8 Pin Ceramic DIP Single Channel Schematic Noteenablein6.neternal0.0to0.bacaacitorirecommendedbetweenCCandgroundoreachackagete. ESD Classification (MIL-STD-883, Method 3015) CP0000andCP60 CP0andCP60 (D)Cla (Dot)Cla Recommended Operating Conditions Parameter PowerSuloltage nutCurrentigheveleachchannel nutoltageoweveleachchannel anut(oad)eachchannel Symbol CC N Min. . 0 Max. 0 0. Units m Single Channel Product Only ighevelEnableoltage owevelEnableoltage E E .0 0 0 0. Electrical Characteristics =CtoC.CC0m(N)m0()0.unleotherwieecified. Parameter ogicowututoltage ogicighututoltage Symbol Group A, Sub-groups[11] N ututeakage Current(UCC) Limits Test Conditions =6.m (oad) =.6m (**=CC.) =0.m =. =0 ogic ow Sul Current Single Channel CC CC=. CC=0 CC=. CC=0 CC=. CC=0 CC CC=. CC=0 CC=. CC=0 CC=. CC=0 S =CC= . =CC=0 ogicighShortCircuit ututCurrent nutorwardoltage nutevere Breakdownoltage nutututnulation eakageCurrent ogicighCommonMode ranientmmunit ogicowCommonMode ranientmmunit ProagationDela imetoogicow ProagationDela imetoogicigh S B CC=. CC=0 =m =ND .0 .0 . =m CC= . =0 E= Don't Care = =0 = == =0 =m E= Don't Care == m == == m =0 0 0 . m m . . 9.0 0.6 7 .9 . . 6.6 9 . ** . 00 00 6 7. 0 . 6 9 m m m m Min. Typ.* Max. 0. Units Fig. Notes Dual Channel uad Channel ogic igh Sul Current Single Channel Dual Channel uad Channel ogicowShortCircuit ututCurrent =m =0m =00dct= 6%=C =mCM=0PP =0mCM=0PP |CM| |CM| tP tP 90 90 90 90 000 0000 000 0000 7 0 0 m m n n 9 9 6 6 6 6 7 7 Electrical Characteristics - Single Channel Product Only =CtoC.CC0m(N)m0()0..0E00E0. unleotherwieecified. Parameter ighmedance Stateutut Current Symbol Z Z Group A, Sub-groups[11] Limits Test Conditions =0. =. =. =0 EN= =0 EN= =m Min. Typ.* Max. 0 0 00 00 Units m m Fig. Notes ogicigh Enableoltage ogicow Enableoltage ogicigh EnableCurrent E E E EN=.7 EN=. EN=0 .0 0. 0 00 0.00 0 0. m ogicow EnableCurrent E EN=0. m *llticalvalueareatCC==C(N)=munleotherwieecified. Typical Characteristics llticalvalueareat=CCC=(N)=munleotherwieecified. Parameter nutCurrentterei nutDiodeemerature Coefficient eitance(nututut) Caacitance(nututut) nutCaacitance ututieime(090%) ututallime(900%) Symbol YS D D C CN tr t Test Conditions CC= =m =00dc =Mz =0=Mz Typ. 0.07 . 0 .0 0 0 Units m mC W n n Fig. Notes 0 7 7 Single Channel Product Only ututEnableimetoogicigh ututEnableimetoogicow ututDiableimeromogicigh ututDiableimeromogicow tPZ tPZ tPZ tPZ 0 0 n n n n Multi-Channel Product Only nutnutnulationeakage Current eitance(nutnut) Caacitance(nutnut) C 6% =00t= =00 =Mz 0. 0 . n W 9 9 9 Note . PeakorwardnutCurrentulewidth<0atzmaimumreetitionrate. . Eachchanneloamultichanneldevice. . Durationooututhortcircuittimenottoeceed0m. . lldeviceareconideredtwoterminaldevicemeauredbetweenallinutleadorterminalhortedtogetherandalloututleadorter minalhortedtogether. . hiiamomentarwithtandtetnotanoeratingcondition. 6. CMithemaimumrateorieothecommonmodevoltagethatcanbeutainedwiththeoututvoltageinthelogiclowtate(<0. ).CMithemaimumrateoallothecommonmodevoltagethatcanbeutainedwiththeoututvoltageinthelogichightate( .0). 7. tProagationdelaimeauredromthe0%ointontheleadingedgeotheinutuletothe.ointontheleadingedgeothe oututule.hetProagationdelaimeauredromthe0%ointonthetrailingedgeotheinutuletothe.ointonthe trailingedgeotheoututule. . Meauredbetweeneachinutairhortedtogetherandalloututconnectionorthatchannelhortedtogether. 9. Meauredbetweenadjacentinutairhortedtogetheroreachmultichanneldevice. 0.ZerobiacaacitancemeauredbetweentheEDanodeandcathode. .Standardartreceive00%tetingatC(Subgrouand9).SMDClaandClaartreceive00%tetingatand-C (Subgrouand9and0andreectivel). .Parameteraretetedaartodeviceinitialcharacterizationandaterdeignandrocechange.Parameterguaranteedtolimiteci fiedoralllotnotecificallteted. 10 Figure 1. Typical Logic Low Output Voltage vs. Temperature. Figure 2. Typical Logic High Output Current vs. Temperature. Figure 3. Output Voltage vs. Forward Input Current. Figure 4. Typical Diode Input Forward Characteristic. V CC PULSE GEN. t r = t f = 5 ns t = 100 kHz 10 % DUTY CYCLE INPUT MONITORING NODE Rf IF OUTPUT VO MONITORING NODE V CC VO CL= 15 pF 5K D1 D.U.T. 5V 619 VE GND D2 D3 D4 THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C L . Figure 5. Test Circuit for tPLH, tPHL, tr, and tf. 11 Figure 6. Typical Propagation Delay vs. Temperature. Figure 7. Typical Rise, Fall Time vs. Temperature. PULSE GENERATOR Z O = 50 t r = t f = 5 ns C L = 15 pF INCLUDING PROBE AND JIG CAPACITANCE. V CC D.U.T. V CC VO D1 +5 V S1 619 IF VO CL VE GND INPUT VO MONITORING NODE D2 5 K D3 D4 S2 Figure 8. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL. A D.U.T. B R IN VCC VO VCC OUTPUT VO MONITORING NODE V FF VE GND 0.1 F BYPASS V CM + PULSE GEN. Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. 1 V CC1 (+5 V) 665 D.U.T. VCC DATA INPUT VO TTL OR LSTTL VE GND TOTEM POLE OUTPUT GATE V CC2 5V 10 V 15 V 20 V RL 1.1 K 2.37 K 3.83 K 5.11 K RL V CC2 (4.5 TO 20 V) V CC1 (+5 V) 750 D.U.T. V CC DATA INPUT TOTEM POLE OUTPUT GATE TTL OR LSTTL CMOS DATA OUTPUT GND 1 2 Figure 10. LSTTL to CMOS Interface Circuit. Figure 11. Recommended LED Drive Circuit. V CC1 (+5 V) 619 D.U.T. V CC 4.02 K DATA INPUT TTL OR LSTTL GND OPEN COLLECTOR GATE Figure 12. Series LED Drive with Open Collector Gate (4.02 k Resistor Shunts IOH from the LED). V CC2 (+5 V) DATA OUTPUT V CC1 (+5 V) 665 665 D.U.T. V CC DATA INPUT TOTEM POLE OUTPUT GATE TTL OR LSTTL UP TO 16 LSTTL LOADS OR 4 TTL LOADS 0.1 F DATA OUTPUT DATA INPUT 1 TOTEM POLE OUTPUT GATE TTL OR LSTTL GND UP TO 16 LSTTL LOADS OR 4 TTL LOADS 1 Figure 13. Recommended LSTTL to LSTTL Circuit. 2 V CC + 20 V D.U.T.* IF +V IN 1.90 V 100 V CC IO VE GND 1200 0.01 F MIL-PRF-38534 Class H, Class K, and DSCC SMD Test Program vago echnologie' iel tocouler are in com liance with MP Clae and . Cla and Cla device are alo in comliance with DSCC drawing9676and96769. eting conit o 00% creening and qualit conor manceinectiontoMP. CONDITIONS: I F = 8 mA IO = -14 mA T A = +125 C *ALL CHANNELS TESTED SIMULTANEOUSLY. Figure 14. Single Channel Operating Circuit for Burn-in and Steady State Life Tests. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 2006 Avago Technologies Limited. All rights reserved. 5989-2666EN - April 4, 2007 |
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